The present invention relates to semiconductor fabrication and, more specifically, to providing a method to avoid over polish of the overburden removal step, thereby providing interconnects having lower electrical resistivity and better reliability.
As is well understood in the art, semiconductor chip fabrication traditionally includes a Front-End-Of-the-Line (FEOL) stage, followed by a Middle-Of-the-Line (MOL) stage and then a Back-End-Of-the-Line (BEOL) stage. Typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation, which is basically the fabrication of electronic components in the wafer substrate. The MOL stage is mainly for gate contact formation, and BEOL is the stage in which the individual devices and components (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, which is to say that BEOL fabricates a plurality of metallization layers. A chip will typically have one layer of devices/components fabricated during FEOL but can have up to twelve or more metallization layers implemented in BEOL.
The present invention addresses a problem of semiconductor device fabrication related to the resistivity and reliability of the interconnect structures formed during BEOL processing.
FIG. 1A shows a post copper (Cu) plating and thermal annealing stage of one interconnect 102 of typically many interconnects in one metallization layer of typically several metallization layers formed in a conventional BEOL fabrication process. As shown, interconnect 102 has been filled in by a Cu deposition with the Cu overburden 104 still present. Metallic liner 106 not only prevents Cu migration into the underlying dielectric layer that envelopes interconnect 102 in this metallization layer but also provides better adhesion for the subsequently-deposited electrical conducting material (e.g., Cu), as compared to a common insulator. Metallic liner 106 is typically TaN, which is a conductive material. The area 114 in the metallization layer that surrounds the interconnect 102 is often referred to as the field area.
The overburden 104, typically between approximately 500 A to 1000 nm in thickness, is critical for promoting the grain growth into the patterned feature 102 during the post metal fill thermal anneal process. As shown in FIG. 1A, because of the mechanism by which grain growth occurs during the post metal fill and thermal annealing, larger grains 108 occur in the overburden area and top portion of the pattern feature 102, whereas smaller grains 112 remain in the bottom portion of the feature 102. FIG. 1B shows how the conventional BEOL fabrication step of chemical/mechanical polishing (CMP) will intentionally over polish in order to not only remove the Cu overburden 104 but also to ensure that the metallic liner 106 is removed from the field area 114.
Thus, the conventional polishing for chips with the conductive metallic liner 106 uses a two-step polishing technique. First, the Cu overburden 104 is removed, and this first stage stops when a polishing rate difference is detected by reason of polishing TaN in the metallic liner 106 in addition to the Cu in the overburden 104. The second step is a timed polishing that removes the conductive liner 106 from the field area, plus a certain amount of further intentional over polish, to ensure that no residual is left anywhere on the wafer, since such residual of TaN, previously noted to be conductive, would cause problems in subsequent fabrication steps and/or degrade or destroy features and/or functions of a chip.
The present invention notes that, in comparing the crystal structures in the cross sectional views of FIG. 1A and FIG. 1B, the conventional method of over polishing has left only the smaller Cu grains 112 in the interconnect structure 102. The larger Cu grains 108 that had been present in the upper portion of the interconnect structure 102 have been polished off during the second polishing stage, intended to ensure that the metallic liner 106 has been completely removed from the field area 114.
The present invention also recognizes that, due to contribution of resistivity increase from electron scattering at grain boundaries, the feature of having only these remaining small-grain Cu grains 112 at the bottom of the interconnect 102 is not so desirable since these remaining small grains 112 leave the interconnect structure 102 with a higher electrical resistivity than would result if at least some of the larger Cu grains 108 previously present in the upper portion could somehow be retained.
Finally, it is also noted that, although Cu is used as the metal fill in the exemplary discussion above, other metal fill material could be used, depending upon which specific technology is involved. Non-limiting examples of other metals that can be used in certain technical applications include any of cobalt (Co), ruthenium (Ru), tungsten (W), aluminum (Al), nickel (Ni), rhodium (Rh), and/or iridium (Ir). The techniques of the present invention apply equally to any of these other metal fill materials.